1. Field of the Invention
The present invention is related to the field of circuit design. In particular, the present invention is related to method and apparatus to analyze noise in a pulse logic digital circuit design.
2. Description of the Related Art
Static signal integrity analysis is typically used during the design verification stages of an electronic circuit to ensure the functionality of the silicon comprising the circuit for various electrical noise conditions. A noise problem in the design verification state of the electronic circuit may cause functional errors or may impact the frequency performance of the electronic circuit.
FIG. 1 illustrates an example of a conventional pulse logic digital circuit. Pulse logic circuits are circuits used to maximize the performance of digital circuits and work using a pull-up/pull down network. As illustrated in FIG. 1, the example pulse logic digital circuit 100 comprises a PMOS transistor 105 coupled to NMOS transistors 110-125 as illustrated. The signal value at node N1 is maintained by a keeper circuit comprising back to back inverters 130 and 135 as illustrated. The clock signal CLK is inverted by inverter 140 to form the NCLK signal. The CLK signal and the NCLK signal is input into the gates of transistors 110 and 120 respectively. When CLK is 0 the PMOS transistor 105 is on and precharges node N1 to a logical 1. At this time NMOS 110 is off and therefore, the voltage value at N1 is maintained at 1. Assuming a logical 1 at inputs A and B of NMOS transistors 115 and 125 respectively, during the transition of CLK from 0 to 1, NMOS transistor 110 is turned on and NMOS transistor 120 is turns off after an inverter delay. Thus, during the inverter delay all NMOS transistors 110-125 are turned on, discharging node N1 to a logical 0, and this results in a logical 1 at the output of the keeper. Thus, for the circuit of FIG. 1, only when both transistors 115 and 125 have a 1 bat their inputs the output of the pulse logic digital circuit is a 1.
Conventional verification tools are incapable of accurately analyzing pulse logic digital circuits because the conventional verification tools either simplify the circuit to an equivalent circuit or are unable to generate a steady state stimuli condition which tests the node N1 under evaluation conditions. For example, the conventional verification tools may simplify FIG. 1 to an AND gate coupled to a latch and apply steady state signals to inputs of the equivalent circuit to analyze noise effects. Simplifying and/or analyzing pulse logic digital circuits using steady state signals is inaccurate, because during normal operation, the pulse logic digital circuits latch the signals at node N1 during the inverter delay i.e., during a transition of the CLK signal as illustrated with respect to FIG. 1. Thus, conventional verification tools fail to indicate problems such as noise related failures in pulse logic digital circuits.